The FORCE-A20 signal is well-known in the art as a signal (typically provided from an output pin of an 8042 keyboard controller) for forcing low the A20 address line of an advanced "host" microprocessor (e.g., an 80286 or 80386 microprocessor) in response to a command from the advanced host microprocessor. As such, the advanced host microprocessor can execute (in real mode) software written to be executed by a less advanced, 8086, microprocessor.
In particular, the address space of the 8086 microprocessor is limited address to being addressed by twenty address lines (i.e., A0-A19) while the advanced microprocessor has more than twenty address lines. By forcing the A20 address line of the advanced microprocessor low, the advanced microprocessor can simulate the "wrap-around" feature employed by some 8086 software. The "wrap-around" feature is discussed in detail in the background portion of U.S. Pat. No. 5,381,530 to Thayer et al. (issued Jan. 10, 1995) and hereby incorporated by reference in its entirety.
In addition, the RESET-CPU signal is well-known in the art as a signal also provided from an output pin of a keyboard controller for addressing the reset input of an advanced microprocessor. This allows the advanced microprocessor to switch from switch from "protected mode" to "real mode". This is also discussed in the background portion of U.S. Pat. No. 5,381,530.
A problem with employing a keyboard controller to implement the FORCE-A20 and RESET-CPU commands is that the keyboard controller's primary function is to control communication with external input/output devices, and the FORCE-A20 and RESET-CPU commands should be handled without affecting this communication. For example, the keyboard controller may communicate with external devices via a "PS/2 protocol". (In addition, the keyboard controller may provide an interface to other devices such as a "smart battery" via a power management bus.) Significantly, if a PS/2 protocol data packet transfer is interrupted (e.g., in the prior art by a command being received by the keyboard controller from the host processor), the data transfer must be re-initiated from the beginning. This is illustrated in FIG. 1-1. Ideally, a 1-2 ms uninterrupted time period is required to properly service a PS/2 transfer. In addition, as host processors become faster, the period between FORCE-A20 commands shrinks, further shrinking the uninterrupted periods available to the keyboard controller to properly service PS/2 transfers.
If the external input/output device is a mouse and the communication with the mouse is interrupted for too long a period, this could result in mouse "sticking" or "jumping". On the other hand, the keyboard controller must handle the FORCE-A20 and RESET-CPU commands in a timely manner since the host processor cannot continue processing after a FORCE-A20 or RESET-CPU command has been issued until the keyboard controller has actually handled the command by asserting the appropriate output.